PATN Patent Bibliographic Information
WKU Patent Number: 05336936
SRC Series Code: 7
APN Application Number: 8799644
APT Application Type: 1
ART Art Unit: 259
APD Application Filing Date: 19920506
TTL Title of Invention: One-transistor adaptable analog storage element and array
ISD Issue Date: 19940809
NCL Number of Claims: 2
ECL Exemplary Claim Number: 1
EXA Assistant Examiner: Santamauro; Jon
EXP Primary Examiner: Westin; Edward P.
NDR Number of Drawings Sheets: 7
NFG Number of Figures: 11

INVT Inventor Information
NAM Inventor Name: Allen; Timothy P.
CTY Inventor City: Los Gatos
STA Inventor State: CA

INVT Inventor Information
NAM Inventor Name: Cser; James B.
CTY Inventor City: Santa Clara
STA Inventor State: CA

ASSG Assignee Information
NAM Assignee Name: Synaptics, Incorporated
CTY Assignee City: San Jose
STA Assignee State: CA
COD Assignee Type Code: 02

CLAS Classification
OCL Original U.S. Classification: 307201
XCL Cross Reference Classification: 395 24
XCL Cross Reference Classification: 365185
XCL Cross Reference Classification: 307450
EDF International Classification Edition Field: 5
ICL International Classification: H03K 1908
ICL International Classification: H03K 19094
FSC Field of Search Class: 307
FSS Field of Search Subclass: 201;529;465;450
FSC Field of Search Class: 395
FSS Field of Search Subclass: 24
FSC Field of Search Class: 365
FSS Field of Search Subclass: 185

LREP Legal Information
FRM Legal Firm: D'Alessandro, Frazzini & Ritchie

ABST Abstract

An analog storage array according to the present invention is disposed on a
semiconductor substrate. The array is arranged as a plurality of rows and
a plurality of columns and includes a plurality of N-channel MOS
transistors disposed in the rows and columns in a p-well in the
semiconductor substrate. Each of the MOS transistors includes a source, a
drain, and a floating gate forming a tunneling junction with a tunneling
electrode. An input line is associated with each of the rows in the array.
Each input line is connected to the source of each of the N-channel MOS
transistors disposed in the row with which the input line is associated. A
bias line is associated with each of the rows in the array. Each bias line
is capacitively coupled to the floating gate of each of the N-channel MOS
transistors disposed in the row with which the bias line is associated. A
tunnel line is associated with each of the columns in the array. Each
tunnel line connected to the tunneling electrode of each of the N-channel
MOS transistors disposed in the column with which the bias line is
associated. A current-sum line is associated with each of the columns in
the array. Each current-sum line is connected to the drain of each of the
N-channel MOS transistors disposed in the column with which the bias line
is associated. Circuitry is provided for forward biasing said p-well with
respect to the substrate. Circuitry is provided for simultaneously driving
a selected one of the bias lines low while driving a selected one of the
tunnel lines high, for raising the floating gate voltage of the one of the
N-channel MOS transistors common to the selected one of the bias lines and
the selected one of the tunnel lines.

BSUM Brief Summary

BACKGROUND OF THE INVENTION

1. Field Of The Invention

The present invention relates to analog storage elements and arrays
generally. More particularly, the present invention relates to an
adaptable one-transistor analog storage element and an adaptable analog
storage array comprising a plurality of one-transistor analog storage
elements.

2. The Prior Art

Floating gate MOS transistors have been utilized in digital memory
applications for over a decade. More recently, floating gate MOS
technology has found use in analog applications. For example, in U.S. Pat.
Nos. 4,890,259 and 4,989,179, analog floating gate devices are employed in
an analog signal recording and playback system.

Many schemes have been proposed to use floating gate structures as weight
storage for analog neural networks. Any such network requires a synaptic
update mechanism which allows the weight to be changed depending on the
combination of an input signal and an error signal. The desirable
properties of such an update mechanism when implemented in an analog
integrated circuit are small size, ability to work continuously (i.e., to
use the signal while it is being updated), and freedom from high-voltage
circuitry requirements within the synapse cell itself. The learning rate
of such an update mechanism should not vary widely between circuits on the
same chip.

In U.S. Pat. Nos. 4,935,702, and 5,068,622 to Mead et al., floating gate
technology is used to control random offsets in analog amplifier elements.
In U.S. Pat. No. 4,953,928 to Anderson et al., analog floating gates are
employed in devices for performing the long term learning function. In
U.S. Pat. No. 5,059,920 to Anderson et al., analog floating gates are
employed in conjunction with devices containing electron injection and
tunneling structures for performing an electrical learning function. In
U.S. Pat. No. 5,083,044 to Mead et al., a synaptic element and array
employ analog floating gate technology.

The prior art described in U.S. Pat. No. 5,059,920, and developed more
recently by Mead et al. in co-pending application Ser. No. 07/805,324,
filed Dec. 10, 1991, required rather complex structures occupying
considerable area on the silicon surface. It would be desirable to further
improve upon the devices disclosed in these references by providing
similar functionality in structures utilizing less integrated circuit area
per synapse.

Accordingly, it is an object of the present invention to provide a
one-transistor synapse in a neural network.

It is a further object of the present invention to provide an array of
synaptic elements, each containing only one transistor, the floating gate
of any of which elements can be selectively either increased or decreased
without appreciably disturbing the weights of other elements in the array.

A further object of the present invention is to provide a neural network
including a plurality of synapses which occupies a smaller area than
possible with prior art arrays.

This and other objects of the invention will be apparent to any person of
ordinary skill in the art from the description of the invention contained
herein.

BRIEF DESCRIPTION OF THE INVENTION

According to a first aspect of the present invention, a one-transistor
analog synaptic element comprises an N-channel MOS transistor including a
source, a drain, and a floating gate forming a tunneling junction with a
tunneling electrode. The single transistor synapse is preferably disposed
in a p-well in an n-type substrate and can be biased such that electrons
may be both placed onto and removed from the floating gate.

According to a second aspect of the present invention, a synaptic array of
one-transistor analog synaptic elements according to the present invention
are disposed on a semiconductor substrate. The array is arranged as a
plurality of rows and a plurality of columns and includes a plurality of
N-channel MOS transistors disposed in the rows and columns in a p-type
semiconductor substrate, which may comprise a p-well in an n-type
semiconductor substrate. Each of the MOS transistors includes a source, a
drain, and a floating gate. The floating gate forms a tunneling junction
with a tunneling electrode.

An input line is associated with each of the rows in the array. Each input
line is connected to the source of each of the N-channel MOS transistors
disposed in the row with which the input line is associated.

A bias line is associated with each of the rows in the array. Each bias
line is capacitively coupled to the floating gate of each of the N-channel
MOS transistors disposed in the row with which the bias line is
associated.

A tunnel line is associated with each of the columns in the array. Each
tunnel line is connected to the tunneling electrode of each of the
N-channel MOS transistors disposed in the column with which the tunnel
line is associated.

A current-sum line is associated with each of the columns in the array.
Each current-sum line is connected to the drain of each of the N-channel
MOS transistors disposed in the column with which the current-sum line is
associated.

Means are provided for simultaneously driving one or more of the bias lines
low while driving one or more of the tunnel lines high, for raising the
floating gate voltage of the one or more of the N-channel MOS transistors
common to the selected bias lines and the selected tunnel lines. In this
way, tunneling may be induced at one or more of the tunneling junctions.

Means are provided for forward biasing the substrate with respect to the
well to cause minority electrons to be injected into the p-well and to a
depletion layer associated with the active regions of the N-channel MOS
transistors, and for selectively raising the drain and source voltages of
one or more of the transistors to accelerate the injected electrons enough
to enable them to enter the gate oxide and migrate onto the floating gate.

CLMS Claims
STM Claim Statement: What is claimed is:
NUM Claim Number: 1.

1. An analog storage array comprising a plurality of cells arranged as a
plurality of rows and a plurality of columns, said array disposed on an
n-type semiconductor substrate and including:

a p-type well disposed in said n-type substrate;

a plurality of N-channel MOS transistors disposed in said rows and columns
in said p-type well of said n-type semiconductor substrate, a single one
of said N-channel MOS transistors comprising each cell, each of said
N-channel MOS transistors including a source, a drain, and a floating gate
forming a tunneling junction with a tunneling electrode;

an input line associated with each of said rows, each input line connected
to the source of each of the N-channel MOS transistors disposed in the row
with which the input line is associated;

a bias line associated with each of said rows, each bias line capacitively
coupled to the floating gate of each of the N-channel MOS transistors
disposed in the row with which the bias line is associated;

a tunnel line associated with each of said columns, each tunnel line
connected to the tunneling electrode of each of the N-channel MOS
transistors disposed in the column with which the bias line is associated;

a current-sum line associated with each of said columns, each current-sum
line connected to the drain of each of the N-channel MOS transistors
disposed in the column with which the bias line is associated;

means for forward biasing said p-well with respect to said substrate in
order to inject minority electrons into said p-well; and

means for selectively raising the drain and source voltages of a selected
one of said N-channel floating gate transistors to accelerate the said
injected minority electrons enough to enable them to migrate onto the
floating gate of said selected one of said N-channel floating gate
transistors; and

means for simultaneously driving a selected one of said bias lines low
while driving a selected one of said tunnel lines high, for causing
electron tunneling from the floating gate of the one of the N-channel MOS
transistors common to said selected one of said bias lines and said
selected one of said tunnel lines.
NUM Claim Number: 2.

2. An analog storage array comprising a plurality of cells arranged as a
plurality of rows and a plurality of columns, said array disposed on an
n-type semiconductor substrate and including:

a p-type well disposed in said n-type substrate;

a plurality of N-channel MOS transistors disposed in said rows and columns
in said p-type well of said n-type semiconductor substrate, a single, one
of said N-channel MOS transistors comprising each cell, each of said
N-channel MOS transistors including a source, a drain, and a floating gate
forming a tunneling junction with a tunneling electrode;

an input line associated with each of said rows, each input line connected
to the source of each of the N-channel MOS transistors disposed in the row
with which the input line is associated;

means for forward biasing said p-well with respect to said substrate in
order to inject minority electrons into said p-well; and

means for simultaneously raising the drain and source voltages of at least
one of said N-channel floating gate transistors to accelerate the said
injected minority electrons enough to enable them to migrate onto the
floating gates of said at least one of N-channel floating gate
transistors; and

means for simultaneously driving selected ones of said bias lines low while
driving selected ones of said tunnel lines high, for causing electron
tunneling from selected ones of the floating gates of said N-channel MOS
transistors.